1. Field of the Invention
The present invention relates to an active matrix device, for example for use as a display. The device may comprise a liquid crystal active matrix display implemented using thin film transistor (TFT) techniques, for example based on amorphous silicon or high or low temperature poly-silicon. Such displays may be used in portable battery-powered equipment.
2. Description of the Related Arts
FIG. 1 of the accompanying drawings illustrates a conventional type of active matrix device comprising an active matrix 1 of N rows and M columns of picture elements (pixels) such as 2. The pixels of each column are connected to a data line driver 3 by a respective data line such as 4. The data line driver 3 has an input 5 for receiving timing, control and data signals.
The pixels of each row are connected by a respective scan line such as 6 to a scan line driver 7. The scan line driver 7 is synchronised by the timing signals from the input 5 and activates one scan line 6 at a time in a repeating sequence.
FIG. 2 of the accompanying drawings illustrates four active matrix pixels of known type. Each pixel comprises a TFT 10 whose gate is connected to the scan line 6 and whose source is connected to the data line 4. The drain of the TFT 10 is connected to a pixel electrode 11 and to a first terminal of a storage capacitor 12, whose second terminal is connected to a common electrode line 13 which is shared by all of the storage capacitors 12 of the same row of pixels. The common electrode lines 13 of all of the rows are connected to a common DC supply voltage.
In use, the TFTs 10 of the pixels act as switches with the switching being controlled by the signals on the scan lines 6. Each pixel 2 of the active matrix is then updated at a frequency known as the frame rate. Updating of a single frame of image data is generally performed on a row-by-row basis. For each row of pixels, the data line driver 3 receives a row of image data to be displayed and charges the M data lines 4 to the corresponding analogue voltages. The scan line driver 7 activates one of the scan lines 6 so that all of the TFTs 10 connected to the activated scan line are switched on. The TFTs 10 transfer charge from the data lines 4 to the storage capacitors 12 until the voltage across each capacitor is equal to the voltage on the data line. The scan line driver 7 then deactivates the row of TFTs 10, whose source-drain paths return to a high impedance state.
Active matrix addressing may be further sub-divided into two categories, namely panel-sample-and-hold addressing (also referred to as point-at-a-time addressing) and line-at-a-time addressing. In the former scheme, the data lines are usually isolated from the data line charging circuits of the data line driver 3 when each scanned line is activated. In the latter scheme, the data lines are normally continuously driven during the scan line activation time.
The non-infinite impedance of each TFT 10 when switched off results in charge flow or leakage between each storage capacitor 12 and the data line 4 for that column. This results in an undesirable change in the voltage at the pixel electrode 11 with consequent impairment of image quality. The magnitude of the voltage change depends on the size of the leakage current, the size of the storage capacitor 12 and the duration between pixel updates i.e. the frame rate.
The leakage current of a TFT can be reduced by device design modifications which require changes to the fabrication process. For example, it is possible to introduce a lightly doped drain (LDD) which, in addition to reducing high drain fields, also increases the channel resistance. Such TFT switch may also be implemented as a dual or triple gate device, effectively putting two or three switches in series between the data line and the pixel electrode. This results in an increase in the channel resistance and a reduction in the “on” performance of the TFTs.
U.S. Pat. No. 5,517,150 discloses an arrangement of the type shown in FIG. 3 of the accompanying drawings. The pixel arrangement differs from that shown in FIG. 2 of the accompanying drawings by the provision of a further TFT 15 whose source-drain path is connected between the drain of the TFT 10 and the pixel electrode 11. Also, a further capacitor 16 in connected between the common line 13 and the connection between the TFTS 10 and 15.
When the scan line 6 for a particular pixel is activated, both of the transistors 10 and 15 are turned on so that both of the capacitors 12 and 16 are charged from the data line 4. When the scan line is deactivated, both transistors are switched off. As described above, the charge leakage through the transistor 10 results in a variation of the voltage across the capacitor 16. However, there is only a very small drop in voltage across the transistor 15 and hence a much smaller leakage current so that there is a much smaller change in voltage across the capacitor 12 and hence at the pixel electrode 11.
Pixel voltage changes caused by charge leakage may be made smaller by increasing the value of the storage capacitor 12. However, the storage capacitor cannot be made arbitrarily large. For example, if the display is of the transmissive type, a large storage capacitor may reduce the pixel aperture ratio and therefore the display brightness. Also, it may not be possible to charge fully a relatively large storage capacitor with a relatively small TFT during the available scan line activation time. For panel-sample-and-hold displays the charge on the data line, which has capacitance Cl, is shared with the storage capacitor, which is of capacitance Cs. As a result, the voltage written to the pixel is not the same as that (V1) sampled onto the data line 4. This Voltage disparity ΔV increases with the capacitance of the storage capacitor and, if it is assumed that the storage capacitor is initially uncharged, is given by the expression:       Δ    ⁢                   ⁢    V    =            Cs              Cs        +        Cl              ⁢    V1  Although it is possible to increase the frame rate in order to minimise the duration for which the pixel voltage has to be held constant, this may not be a practical option. For example, it may not be possible to charge the data lines or storage capacitors during the reduced addressing periods or the power consumption may be increased beyond what is acceptable. For low power applications, it may be desirable to update the active matrix at a relatively low frame rate in order to reduce power consumption.
U.S. Pat. No. 6,023,074 discloses a pixel TFT arrangement similar to that disclosed in U.S. Pat. No. 5,517,150. However, the storage capacitors are implemented as metal-oxide-semiconductor (MOS) capacitors. As shown in FIG. 4 of the accompanying drawings, a MOS capacitor is formed by a transistor 18 whose gate g forms one terminal of the capacitor and whose sources and drain d are connected together to form the other terminal. The connection between the source and drain may be achieved by heavily doped semiconductor rather than by “ohmic” contact connections to a separate interconnect layer. The effective capacitance of the device is voltage dependent an illustrated by the graph in FIG. 4. Below the threshold voltage Vt of the MOS device, the capacitance is equal to the sum of the gate-source and gate-drain overlap capacitances. Above the threshold voltage Vt, the capacitance changes to include the MOS oxide capacitance in addition to the overlap capacitances.
U.S. Pat. No. 5,835,170 discloses an arrangement of the type shown in FIG. 5 of the accompanying drawings, in which the common electrode lines 13 are omitted and the second terminals of the capacitors 12 are connected to the scan line 6 of the adjacent row of pixels. An advantage of such a capacitor-on-gate arrangement is that the total number of horizontal signals traversing the active matrix 1 is halved compared with the arrangement shown in FIG. 2 so that a higher pixel aperture ratio may be achieved. However, the scanning direction of the active matrix 1 is fixed. In particular, the rows or the active matrix must be scanned from the bottom row upwards in FIG. 5.